Recently, as production of digital apparatus has increased with progress of digital signal processing technology, CMOS integrated circuits have been widely used in semiconductor devices provided within the digital apparatus. However, there are cases where it is easier to process high-frequency signals, video signals, audio signals, and the like as analog signals. In addition, to realize A/D converter circuits, D/A converter circuits, clock oscillator circuits, and the like requires analog signal processing.
Bipolar transistors have good suitability as analog signal processing circuits. CMOS has been considered to have low suitability as analog signal processing circuits, except for a part of analog signal processing circuits such as sample-and-hold circuits or the like. However, CMOS inverter circuits, though of a very simple configuration, have advantages of a wide input dynamic range, high gain, excellent current supply capability, and the like. It is expected that reduction of overall circuit scale and improvement of performance will be realized by using a CMOS inverter circuit as an analog signal processing circuit.
FIGS. 13A and 13B are diagrams showing an example of configuration of a CMOS inverter circuit as an analog signal processing circuit. FIG. 13A shows the CMOS inverter circuit itself. FIG. 13B shows a circuit configuration in which a virtual voltage source and the like for providing an ideal operating point in performing analog signal processing are added to facilitate description of operating characteristics of the CMOS inverter circuit. In FIGS. 13A and 13B, reference numeral 201 denotes a voltage source; reference numeral 202 denotes a PMOS transistor; reference numeral 203 denotes an NMOS transistor; reference numeral 204 denotes a ground part; reference numeral 205 denotes an input terminal; reference numeral 206 denotes an output terminal; reference numeral 207 denotes a load resistance determined by drain resistance of the MOS transistors; and reference numeral 208 denotes a voltage source virtually set for bias voltage. Let Vdd be a voltage value of the voltage source 201, Vdd/2 be a voltage value of the voltage source 208, Rd be a resistance value of the load resistance 207, Ip be a drain current of the PMOS transistor 202, In be a drain current of the NMOS transistor 203, Id be a current flowing through the load resistance 207, Vg be a voltage value of an input voltage at the input terminal 205, and Vo be a voltage value of an output voltage at the output terminal 206.
Operating characteristics of the CMOS inverter circuit shown in FIGS. 13A and 13B will next be described. In the case of using the CMOS inverter circuit as an analog signal processing circuit, for as wide an input and an output dynamic range as possible, bias setting is desired to be made such that the output voltage is Vo=Vdd/2 when the input voltage is Vg=Vdd/2. The drain current Ip of the PMOS transistor 202 and the drain current In of the NMOS transistor 203 when such bias setting is made are expressed by an equation (1) and an equation (2), respectively.
                    Ip        =                                            Mp              2                        ⁢                                          (                                  Vdd                  -                  Vg                  -                  Vtp                                )                            2                                =                                    Mp              2                        ⁢                                          (                                  Vg                  -                  Vtp                                )                            2                                                          (        1        )                                In        =                              Mn            2                    ⁢                                    (                              Vg                -                Vtn                            )                        2                                              (        2        )            
where Mp is a drain current coefficient of the PMOS transistor 202; Vtp is a threshold voltage of the PMOS transistor 202; Mn is a drain current coefficient of the NMOS transistor 203; and Vtn is a threshold voltage of the NMOS transistor 203.
As shown in FIG. 13B, the output voltage Vo is determined by the resistance value Rd of the load resistance 207 determined by the drain resistance of the MOS transistors and the current Id flowing through the load resistance. The output voltage Vo is given by an equation (3). To realize proper bias setting, a condition for Vo=Vg=Vdd/2 is given by an equation (4).
                    Vo        =                                            Vdd              2                        +                                          (                                  Ip                  -                  In                                )                            ⁢              Rd                                =                                    Vdd              2                        +            IdRd                                              (        3        )                                Id        =                              Ip            -            In                    =                                                                      Mp                  2                                ⁢                                                      (                                          Vg                      -                      Vtp                                        )                                    2                                            -                                                Mn                  2                                ⁢                                                      (                                          Vg                      -                      Vtn                                        )                                    2                                                      =            0                                              (        4        )            
As shown in the equation (4), Vo=Vg when parameters such as the drain current coefficients Mp and Mn and the threshold voltages Vtp and Vtn of the PMOS transistor 202 and the NMOS transistor 203 coincide with each other. Hence, desired bias setting is realized by equalizing the parameters related to element characteristics of the PMOS transistor 202 and the NMOS transistor 203.
It is known, however, that the parameters related to element characteristics of the PMOS transistor 202 and the NMOS transistor 203 generally vary greatly due to a slight difference in a manufacturing environment occurring in each manufacturing process (such a variation in the element characteristics of the MOS transistors occurs in each manufacturing process. The variation will be hereinafter referred to as a manufacturing variation). Therefore Vo is not equal to Vg. On the basis of variations in the element characteristics, Vo>Vg when Ip>In, and Vo<Vg when Ip<In. Hence, even when the input voltage is set to Vg=Vdd/2 for bias setting, the output voltage Vo deviates from Vdd/2, causing a so-called DC offset.
Thus, because of the DC offset occurring according to the manufacturing variation, a sufficient output dynamic range cannot be obtained, and the CMOS inverter circuit as it is not suitable for use as an analog signal processing circuit such as a high-gain amplifier, a buffer amplifier, or the like.